[all-commits] [llvm/llvm-project] 09a081: [X86][SSE] LowerADDSAT_SUBSAT - avoid X86ISD::BLEN...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 09a081f2213639cf4ea529baa77352ed5f6f18c8
      https://github.com/llvm/llvm-project/commit/09a081f2213639cf4ea529baa77352ed5f6f18c8
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-11-20 (Fri, 20 Nov 2020)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/uadd_sat_vec.ll
    M llvm/test/CodeGen/X86/usub_sat_vec.ll

  Log Message:
  -----------
  [X86][SSE] LowerADDSAT_SUBSAT - avoid X86ISD::BLENDV in UADDSAT/USUBSAT custom lowering

Use the OR(CMP,ADD) / AND(CMP,SUB) patterns like we do on pre-SSE4 targets.

We're still using X86ISD::BLENDV on some AVX targets as we don't do custom lowering for >= 256-bit vectors.

Really this (and combineVSelectWithAllOnesOrZeros) needs moving to DAGCombiner, but pre-SSE42 we see the vXi64 comparison type as a 2 x 32-bits result so we can't just rely on ComputeNumSignBits to give us the 'all bits' result we need.