[all-commits] [llvm/llvm-project] bcd469: [NFC][InstCombine] Add test coverage for `and (sex...

[Roman Lebedev via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: bcd469a9912b63ae912af4e693ad5c9d317fbdbb
      https://github.com/llvm/llvm-project/commit/bcd469a9912b63ae912af4e693ad5c9d317fbdbb
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2020-11-20 (Fri, 20 Nov 2020)

  Changed paths:
    A llvm/test/Transforms/InstCombine/signmask-of-sext-vs-of-shl-of-zext.ll

  Log Message:
  -----------
  [NFC][InstCombine] Add test coverage for `and (sext %x), SIGNMASK`-like pattern


  Commit: a91e96702a3b8ef19afc5b7d2e51ce6b6a7fded9
      https://github.com/llvm/llvm-project/commit/a91e96702a3b8ef19afc5b7d2e51ce6b6a7fded9
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2020-11-20 (Fri, 20 Nov 2020)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
    M llvm/test/Transforms/InstCombine/signmask-of-sext-vs-of-shl-of-zext.ll

  Log Message:
  -----------
  [InstCombine] Fold `and(shl(zext(x), width(SIGNMASK) - width(%x)), SIGNMASK)` to `and(sext(%x), SIGNMASK)`

One less instruction and reducing use count of zext.
As alive2 confirms, we're fine with all the weird combinations of
undef elts in constants, but unless the shift amount was undef
for a lane, we must sanitize undef mask to zero, since sign bits
are no longer zeros.

https://rise4fun.com/Alive/d7r
```
----------------------------------------
Optimization: zz
Precondition: ((C1 == (width(%r) - width(%x))) && isSignBit(C2))
  %o0 = zext %x
  %o1 = shl %o0, C1
  %r = and %o1, C2
=>
  %n0 = sext %x
  %r = and %n0, C2

Done: 2016
Optimization is correct!
```


Compare: https://github.com/llvm/llvm-project/compare/e8dc6e9a3242...a91e96702a3b