[all-commits] [llvm/llvm-project] 6b0fc1: [RISCV] Add MemOperand to the instruction created ...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 6b0fc1f3c161295e6577d4c2237cefcb8e4dd9ba
      https://github.com/llvm/llvm-project/commit/6b0fc1f3c161295e6577d4c2237cefcb8e4dd9ba
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-18 (Wed, 18 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/CodeGen/RISCV/select-optimize-multiple.ll

  Log Message:
  -----------
  [RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot

Differential Revision: https://reviews.llvm.org/D91730