[all-commits] [llvm/llvm-project] 38621c: [VE] Add lvm/svm intrinsic instructions

[Kazushi Marukawa via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 38621c45a8fe8ef6b96f4c92919f6fd35b15f3d6
      https://github.com/llvm/llvm-project/commit/38621c45a8fe8ef6b96f4c92919f6fd35b15f3d6
  Author: Kazushi (Jam) Marukawa <marukawa at nec.com>
  Date:   2020-11-17 (Tue, 17 Nov 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
    M llvm/lib/Target/VE/VEInstrInfo.cpp
    M llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td
    M llvm/lib/Target/VE/VEInstrVec.td
    M llvm/lib/Target/VE/VERegisterInfo.cpp
    A llvm/test/CodeGen/VE/VELIntrinsics/lvm.ll
    M llvm/test/CodeGen/VE/VELIntrinsics/vst.ll

  Log Message:
  -----------
  [VE] Add lvm/svm intrinsic instructions

Add lvm/svm intrinsic instructions and a regression test.  Change
RegisterInfo to specify that VM0/VMP0 are constant and reserved
registers.  This modifies a vst regression test, so update it.
Also add pseudo instructions for VM512 register classes
and mechanism to expand them after register allocation.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D91541