[all-commits] [llvm/llvm-project] 124c93: [RISCV] When matching SROIW, check all 64 bits of ...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 124c93c528758071fccfce68f6b633081a19c226
      https://github.com/llvm/llvm-project/commit/124c93c528758071fccfce68f6b633081a19c226
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-16 (Mon, 16 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rv64Zbb.ll

  Log Message:
  -----------
  [RISCV] When matching SROIW, check all 64 bits of the OR mask

We need to make sure the upper 32 bits are all ones to ensure the result is properly sign extended. Previously we only checked the lower 32 bits of the mask. I've also added a check that the shift amount is less than 32. Without that the original code asserts inside maskLeadingOnes if the SROI check is removed or the SROIW pattern is checked first. I've refactored the code to use early outs to reduce nesting.

I've also updated SLOIW matching with the same changes, but I couldn't find a broken test case with the existing code.

Differential Revision: https://reviews.llvm.org/D90961