[all-commits] [llvm/llvm-project] 1c00d0: [VE] LVLGen sets VL before vector insts

[Simon Moll via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 1c00d096a608da1489cc4e3c1bba9ac5b4732af8
      https://github.com/llvm/llvm-project/commit/1c00d096a608da1489cc4e3c1bba9ac5b4732af8
  Author: Simon Moll <simon.moll at emea.nec.com>
  Date:   2020-11-16 (Mon, 16 Nov 2020)

  Changed paths:
    M llvm/lib/Target/VE/CMakeLists.txt
    A llvm/lib/Target/VE/LVLGen.cpp
    M llvm/lib/Target/VE/VE.h
    M llvm/lib/Target/VE/VETargetMachine.cpp
    A llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll
    M llvm/test/CodeGen/VE/VELIntrinsics/vld.ll
    M llvm/test/CodeGen/VE/VELIntrinsics/vst.ll

  Log Message:
  -----------
  [VE] LVLGen sets VL before vector insts

The VE backend represents vector instructions with an explicit 'i32'
vector length operand.  In the VE ISA, the vector length is always read
from the VL hardware register.  The LVLGen pass inserts 'lvl'
instructions as necessary to set VL to the right value before each
vector instruction.

Reviewed By: kaz7

Differential Revision: https://reviews.llvm.org/D91416