[all-commits] [llvm/llvm-project] 67fa01: [RISCV] Add RORW/ROLW/RORIW/ROLIW test cases that ...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 67fa016ac1e24cd0f32a43d6d2ed43e347f1e74b
      https://github.com/llvm/llvm-project/commit/67fa016ac1e24cd0f32a43d6d2ed43e347f1e74b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-13 (Fri, 13 Nov 2020)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv64Zbbp.ll

  Log Message:
  -----------
  [RISCV] Add RORW/ROLW/RORIW/ROLIW test cases that don't sign extend the result. NFC

This shows that we currently fail to select RORIW/ROLIW.