[all-commits] [llvm/llvm-project] 9ca02d: [RISCV] Add an ANDI to shift amount of FSL/FSR ins...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 9ca02d6fe166e4dcc8e651592883171af47257c9
      https://github.com/llvm/llvm-project/commit/9ca02d6fe166e4dcc8e651592883171af47257c9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-12 (Thu, 12 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbt.ll
    M llvm/test/CodeGen/RISCV/rv64Zbt.ll

  Log Message:
  -----------
  [RISCV] Add an ANDI to shift amount of FSL/FSR instructions

The fshl and fshr intrinsics are defined to modulo their shift amount by the bitwidth of one of their inputs. The FSR/FSL instructions read one extra bit from the shift amount. If that bit is set the inputs are swapped. In order to preserve the semantics of the llvm intrinsics we need to make sure that the extra bit isn't set. DAG combine or instcombine may have removed any mask that was originally present.

We could be smarter here and try to use computeKnownBits to check if the bit is known zero, but wanted to start with correctness.

Differential Revision: https://reviews.llvm.org/D90905