[all-commits] [llvm/llvm-project] 226239: [AArch64][GlobalISel] Port some AArch64 target spe...

[AE via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 22623930903dd7922a0ee06d4f43fc74e0053e3d
      https://github.com/llvm/llvm-project/commit/22623930903dd7922a0ee06d4f43fc74e0053e3d
  Author: Amara Emerson <amara at apple.com>
  Date:   2020-11-10 (Tue, 10 Nov 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64Combine.td
    M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
    M llvm/test/CodeGen/AArch64/mul_pow2.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Port some AArch64 target specific MUL combines from SDAG.

These do things like turn a multiply of a pow-2+1 into a shift and and add,
which is a common pattern that pops up, and is universally better than expensive
madd instructions with a constant.

I've added check lines to an existing codegen test since the code being ported
is almost identical, however the mul by negative pow2 constant tests don't generate
the same code because we're missing some generic G_MUL combines still.

Differential Revision: https://reviews.llvm.org/D91125