[all-commits] [llvm/llvm-project] 73a6cd: [ARM] Add a RegAllocHint for hinting t2DoLoopStart...

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 73a6cd4b6b58184cff1c71cf152b98cc068f544b
      https://github.com/llvm/llvm-project/commit/73a6cd4b6b58184cff1c71cf152b98cc068f544b
  Author: David Green <david.green at arm.com>
  Date:   2020-11-10 (Tue, 10 Nov 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    M llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMInstrThumb2.td
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/exitcount.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/extending-loads.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/sibling-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-disabled-in-loloops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/tp-multiple-vpst.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
    M llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-fma-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-fp16convertloops.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-scatter-ptr-address.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll
    M llvm/test/CodeGen/Thumb2/mve-nounrolledremainder.ll
    M llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll
    M llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-vctpvpsel.ll
    M llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-shifts-scalar.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-vldshuffle.ll
    M llvm/test/CodeGen/Thumb2/mve-vldst4.ll
    M llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll
    M llvm/test/Transforms/HardwareLoops/ARM/calls-codegen.ll
    M llvm/test/Transforms/HardwareLoops/ARM/structure.ll

  Log Message:
  -----------
  [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR

This hints the operand of a t2DoLoopStart towards using LR, which can
help make it more likely to become t2DLS lr, lr. This makes it easier to
move if needed (as the input is the same as the output), or potentially
remove entirely.

The hint is added after others (from COPY's etc) which still take
precedence. It needed to find a place to add the hint, which currently
uses the post isel custom inserter.

Differential Revision: https://reviews.llvm.org/D89883