[all-commits] [llvm/llvm-project] de7195: [AMDGPU][GlobalISel] Fold a chain of two shift ins...

[Mirko Brkušanin via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: de719586a8fa82428bddcb714d00dfa3d0eab526
      https://github.com/llvm/llvm-project/commit/de719586a8fa82428bddcb714d00dfa3d0eab526
  Author: Mirko Brkusanin <Mirko.Brkusanin at amd.com>
  Date:   2020-11-10 (Tue, 10 Nov 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll

  Log Message:
  -----------
  [AMDGPU][GlobalISel] Fold a chain of two shift instructions with constant operands

Sequence of same shift instructions with constant operands can be combined into
a single shift instruction.

Differential Revision: https://reviews.llvm.org/D90217


  Commit: 53ae95c946c0d3a32e402d0815cf2de6c0f8c3d8
      https://github.com/llvm/llvm-project/commit/53ae95c946c0d3a32e402d0815cf2de6c0f8c3d8
  Author: Mirko Brkusanin <Mirko.Brkusanin at amd.com>
  Date:   2020-11-10 (Tue, 10 Nov 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll

  Log Message:
  -----------
  [AMDGPU][GlobalISel] Combine shift + logic + shift with constant operands

This sequence of instructions can be simplified if they are single use and
some operands are constants. Additional combines may be applied afterwards.

Differential Revision: https://reviews.llvm.org/D90223


  Commit: fb36ab0a42f4ea8909c19c9e6759be5d617aef55
      https://github.com/llvm/llvm-project/commit/fb36ab0a42f4ea8909c19c9e6759be5d617aef55
  Author: Mirko Brkusanin <Mirko.Brkusanin at amd.com>
  Date:   2020-11-10 (Tue, 10 Nov 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/Target/AArch64/AArch64Combine.td
    A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll

  Log Message:
  -----------
  [GlobalISel] Expand combine for (x & mask) -> x when (x & mask) == x

We can use KnownBitsAnalysis to cover cases when mask is not trivial. It can
also help with cases when mask is not constant but can still be folded into
one. Since 'and' is comutative we should treat both operands as possible
replacements.

Differential Revision: https://reviews.llvm.org/D90674


  Commit: a75d6178b809cf11d54af91e8e1254064d58f6eb
      https://github.com/llvm/llvm-project/commit/a75d6178b809cf11d54af91e8e1254064d58f6eb
  Author: Mirko Brkusanin <Mirko.Brkusanin at amd.com>
  Date:   2020-11-10 (Tue, 10 Nov 2020)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/Target/AArch64/AArch64Combine.td
    A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll

  Log Message:
  -----------
  [GlobalISel] Add combine for (x | mask) -> x when (x | mask) == x

If we have a mask, and a value x, where (x | mask) == x, we can drop the OR
and just use x.

Differential Revision: https://reviews.llvm.org/D90952


Compare: https://github.com/llvm/llvm-project/compare/d2f7f775cac5...a75d6178b809