[all-commits] [llvm/llvm-project] 4265cb: [RISCV] Make SIGN_EXTEND_INREG from i8/i16 legal w...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 4265cbaa34815f0a6d81f3479f59903f3f2f7bee
      https://github.com/llvm/llvm-project/commit/4265cbaa34815f0a6d81f3479f59903f3f2f7bee
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-09 (Mon, 09 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbb.ll

  Log Message:
  -----------
  [RISCV] Make SIGN_EXTEND_INREG from i8/i16 legal when Zbb extension is enabled.

This produces better code for sign extend to i64 on RV32 target.

Differential Revision: https://reviews.llvm.org/D91023


  Commit: a59076006ba5b12acd1c602bfb67d4a92e17290c
      https://github.com/llvm/llvm-project/commit/a59076006ba5b12acd1c602bfb67d4a92e17290c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-09 (Mon, 09 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbbp.ll
    M llvm/test/CodeGen/RISCV/rv64Zbbp.ll

  Log Message:
  -----------
  [RISCV] Add isel patterns for using PACK for zext.h and zext.w.

Differential Revision: https://reviews.llvm.org/D91024


  Commit: 5d3fd3df94e5463f8460fbc1a643e663b0e6cb2b
      https://github.com/llvm/llvm-project/commit/5d3fd3df94e5463f8460fbc1a643e663b0e6cb2b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-09 (Mon, 09 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbb.ll
    M llvm/test/CodeGen/RISCV/rv64Zbb.ll

  Log Message:
  -----------
  [RISCV] Make ctlz/cttz cheap to speculatively execute so CodeGenPrepare won't insert a zero check.

Add additional isel patterns for ctzw/clzw instructions.

Differential Revision: https://reviews.llvm.org/D91040


Compare: https://github.com/llvm/llvm-project/compare/b22317705d39...5d3fd3df94e5