[all-commits] [llvm/llvm-project] c0dd22: [RISCV] Add isel patterns to match sbset/sbclr/sbi...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c0dd22e44a66cf16768850f7f15d0061ba793c85
      https://github.com/llvm/llvm-project/commit/c0dd22e44a66cf16768850f7f15d0061ba793c85
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-09 (Mon, 09 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbs.ll
    M llvm/test/CodeGen/RISCV/rv64Zbs.ll

  Log Message:
  -----------
  [RISCV] Add isel patterns to match sbset/sbclr/sbinv/sbext even if the shift amount isn't masked.

This uses the shiftop PatFrags to handle the masked shift amount
and unmasked shift amount cases. That also checks XLen as part
of the masked amount check so we don't need separate RV32 and RV64
patterns.

Differential Revision: https://reviews.llvm.org/D91016