[all-commits] [llvm/llvm-project] 9ca6fc: Add a new altera kernel name restriction check to ...

[Frank Derry Wanye via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 9ca6fc4e095f9aacd70e406e640472ad2d370553
      https://github.com/llvm/llvm-project/commit/9ca6fc4e095f9aacd70e406e640472ad2d370553
  Author: Frank Derry Wanye <wanyef at mail.gvsu.edu>
  Date:   2020-11-09 (Mon, 09 Nov 2020)

  Changed paths:
    M clang-tools-extra/clang-tidy/altera/AlteraTidyModule.cpp
    M clang-tools-extra/clang-tidy/altera/CMakeLists.txt
    A clang-tools-extra/clang-tidy/altera/KernelNameRestrictionCheck.cpp
    A clang-tools-extra/clang-tidy/altera/KernelNameRestrictionCheck.h
    M clang-tools-extra/docs/ReleaseNotes.rst
    A clang-tools-extra/docs/clang-tidy/checks/altera-kernel-name-restriction.rst
    M clang-tools-extra/docs/clang-tidy/checks/list.rst
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/Verilog.cl
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/kernel.cl
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/kernel.h
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/other_Verilog.cl
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/otherdir/vhdl.cl
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/otherthing.cl
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/some/dir/kernel.cl
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/some/kernel.cl/foo.h
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/some/verilog.cl/foo.h
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/some/vhdl.cl/foo.h
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/some_kernel.cl
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/somedir/verilog.cl
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/thing.h
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/uppercase/KERNEL.cl
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/uppercase/VHDL.cl
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/uppercase/vERILOG.cl
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/verilog.h
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/vhdl.CL
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/vhdl.h
    A clang-tools-extra/test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/vhdl_number_two.cl
    A clang-tools-extra/test/clang-tidy/checkers/altera-kernel-name-restriction.cpp

  Log Message:
  -----------
  Add a new altera kernel name restriction check to clang-tidy.

The altera kernel name restriction check finds kernel files and include
directives whose filename is "kernel.cl", "Verilog.cl", or "VHDL.cl".
Such kernel file names cause the Altera Offline Compiler to generate
intermediate design files that have the same names as certain internal
files, which leads to a compilation error.

As per the "Guidelines for Naming the Kernel" section in the "Intel FPGA
SDK for OpenCL Pro Edition: Programming Guide."

This reverts the reversion from 43a38a65233039b5e71797a644d41a890f8d7f2b.