[all-commits] [llvm/llvm-project] fc2fe6: [llvm][AArch64] Simplify (and (sign_extend..) #bit...

[Francesco Petrogalli via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: fc2fe6817e1969cad3d51ae13b171e5abc847b39
      https://github.com/llvm/llvm-project/commit/fc2fe6817e1969cad3d51ae13b171e5abc847b39
  Author: Francesco Petrogalli <francesco.petrogalli at arm.com>
  Date:   2020-11-09 (Mon, 09 Nov 2020)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
    A llvm/test/CodeGen/ARM/and-sext-combine.ll

  Log Message:
  -----------
  [llvm][AArch64] Simplify (and (sign_extend..) #bitmask).

Fold

    VT = (and (sign_extend NarrowVT to VT) #bitmask)

into

    VT = (zero_extend NarrowVT)

With this combine, the test replaces a sign extended load + an
unsigned extention with a zero extended load to render one of the
operands of the last multiplication.

  BEFORE                       |  AFTER
    f_i16_i32:                 |    f_i16_i32:
         .fnstart              |           .fnstart
         ldrsh   r0, [r0]      |           ldrh    r1, [r1]
         ldrsh   r1, [r1]      |           ldrsh   r0, [r0]
         smulbb  r0, r1, r0    |           smulbb  r0, r0, r1
         uxth    r1, r1        |           mul     r0, r0, r1
         mul     r0, r0, r1    |           bx      lr
         bx      lr            |

Reviewed By: resistor

Differential Revision: https://reviews.llvm.org/D90605