[all-commits] [llvm/llvm-project] 93b997: [AArch64] Add pipeline model for HiSilicon's TSV110

[Elvina Yakubova via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 93b99728b1676d23ab5dabc606344230d25e7f4b
      https://github.com/llvm/llvm-project/commit/93b99728b1676d23ab5dabc606344230d25e7f4b
  Author: Elvina Yakubova <elvina.yakubova at huawei.com>
  Date:   2020-11-07 (Sat, 07 Nov 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64.td
    A llvm/lib/Target/AArch64/AArch64SchedTSV110.td
    M llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
    M llvm/test/CodeGen/AArch64/preferred-function-alignment.ll

  Log Message:
  -----------
  [AArch64] Add pipeline model for HiSilicon's TSV110

This patch adds the scheduling and cost model for TSV110.

Reviewed by: SjoerdMeijer, bryanpkc

Differential Revision: https://reviews.llvm.org/D89972