[all-commits] [llvm/llvm-project] 741b04: [RISCV] Only enable GPR<->FPR32 bitconvert isel pa...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 741b04b0b7912611a8a5b7e74462e87b8930a116
      https://github.com/llvm/llvm-project/commit/741b04b0b7912611a8a5b7e74462e87b8930a116
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-05 (Thu, 05 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td

  Log Message:
  -----------
  [RISCV] Only enable GPR<->FPR32 bitconvert isel patterns on RV32. NFCI

Bitconvert requires the bitwidth to match on both sides. On RV64
the GPR size is i64 so bitconvert between f32 isn't possible. The
node should never be generated so the pattern won't ever match, but
moving the patterns under IsRV32 makes it more obviously impossible.
It also moves it to a similar location to the patterns for the
custom nodes we use for RV64.