[all-commits] [llvm/llvm-project] 1938b6: [mlir][spirv] Allow usage of vector size 8 and 16 ...

[abialas1 via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 1938b61bda50f0117e6b8bbc02e42d065d59b4f9
      https://github.com/llvm/llvm-project/commit/1938b61bda50f0117e6b8bbc02e42d065d59b4f9
  Author: Artur Bialas <artur.bialas at intel.com>
  Date:   2020-11-05 (Thu, 05 Nov 2020)

  Changed paths:
    M mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td
    M mlir/lib/Dialect/SPIRV/SPIRVTypes.cpp
    M mlir/test/Dialect/SPIRV/Serialization/ocl-ops.mlir
    M mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
    M mlir/test/Dialect/SPIRV/ops.mlir

  Log Message:
  -----------
  [mlir][spirv] Allow usage of vector size 8 and 16 with Vector16 capability

Per spec, vector sizes 8 and 16 are allowed when Vector16 capability is present.
This change expands the limitation of vector sizes to accept these sizes.

Differential Revision: https://reviews.llvm.org/D90683


  Commit: f9dca1039a4aa06d0449666888a6bc18b2572159
      https://github.com/llvm/llvm-project/commit/f9dca1039a4aa06d0449666888a6bc18b2572159
  Author: Artur Bialas <artur.bialas at intel.com>
  Date:   2020-11-05 (Thu, 05 Nov 2020)

  Changed paths:
    M mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td
    M mlir/include/mlir/Dialect/SPIRV/SPIRVCompositeOps.td
    M mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp
    M mlir/test/Conversion/VectorToSPIRV/simple.mlir
    M mlir/test/Dialect/SPIRV/Serialization/composite-op.mlir
    M mlir/test/Dialect/SPIRV/composite-ops.mlir

  Log Message:
  -----------
  [mlir][spirv] Add VectorExtractDynamicOp and vector.extractelement lowering

VectorExtractDynamicOp in SPIRV dialect
conversion from vector.extractelement to spirv VectorExtractDynamicOp

Differential Revision: https://reviews.llvm.org/D90679


Compare: https://github.com/llvm/llvm-project/compare/5fd3193c88d8...f9dca1039a4a