[all-commits] [llvm/llvm-project] cc3bf2: [RISCV] Remove assertsexti32 from fslw/fsrw isel p...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: cc3bf270776bc362e4a504a2f1bc3c8c932111ea
      https://github.com/llvm/llvm-project/commit/cc3bf270776bc362e4a504a2f1bc3c8c932111ea
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-04 (Wed, 04 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td

  Log Message:
  -----------
  [RISCV] Remove assertsexti32 from fslw/fsrw isel patterns.

The operations in these patterns shouldn't be effected by sign
bits. And the pattern is starting from a sign_extend_inreg so
we aren't expecting sign bits to be passed through either.

Differential Revision: https://reviews.llvm.org/D90739