[all-commits] [llvm/llvm-project] d47300: [RISCV] Correct the operand order for fshl/fshr to...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d47300f503c90511304e4999182060b8e1e86b0f
      https://github.com/llvm/llvm-project/commit/d47300f503c90511304e4999182060b8e1e86b0f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-04 (Wed, 04 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv32Zbb.ll
    M llvm/test/CodeGen/RISCV/rv32Zbbp.ll
    M llvm/test/CodeGen/RISCV/rv32Zbt.ll
    M llvm/test/CodeGen/RISCV/rv64Zbt.ll

  Log Message:
  -----------
  [RISCV] Correct the operand order for fshl/fshr to fsl/fsr instructions.

fsl/fsr take their shift amount in $rs2 or an immediate. The
sources are $rs1 and $rs3.

fshl/fshr ISD opcodes both concatenate operand 0 in the high bits and
operand 1 in the lower bits. fshl returns the high bits after
shifting and fshr returns the low bits. So a shift amount of 0
returns operand 0 for fshl and operand 1 for fshr.

fsl/fsr concatenate their operands in different orders such that
$rs1 will be returned for a shift amount of 0. So $rs1 needs to
come from operand 0 of fshl and operand 1 of fshr.

Differential Revision: https://reviews.llvm.org/D90735