[all-commits] [llvm/llvm-project] 0122a4: [RISCV] Remove assertsexti32 from inputs to riscv_...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 0122a4ea661db4c2509143a4035c8857eedd9aa5
      https://github.com/llvm/llvm-project/commit/0122a4ea661db4c2509143a4035c8857eedd9aa5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-04 (Wed, 04 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td

  Log Message:
  -----------
  [RISCV] Remove assertsexti32 from inputs to riscv_sllw/srlw nodes in B extension isel patterns.

riscv_sllw/srlw only reads the lower 32 bits of the first operand.
And the lower 5 bits of the second operands. Whether the upper
32 bits of the input are sign bits or not doesn't matter.

Also use ineg and not to shorten the patterns.

Differential Revision: https://reviews.llvm.org/D90668