[all-commits] [llvm/llvm-project] 857563: [RISCV] Check all 64-bits of the mask in SelectRORIW.

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 857563eaf02f7aa3cc3748e2c36b45ae14294bf8
      https://github.com/llvm/llvm-project/commit/857563eaf02f7aa3cc3748e2c36b45ae14294bf8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-04 (Wed, 04 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rv64Zbbp.ll

  Log Message:
  -----------
  [RISCV] Check all 64-bits of the mask in SelectRORIW.

We need to ensure the upper 32 bits of the mask are zero.
So that the srl shifts zeroes into the lower 32 bits.

Differential Revision: https://reviews.llvm.org/D90585