[all-commits] [llvm/llvm-project] f09933: [NFC][Reassociate] Add tests with `add`-like `or` ...

[Roman Lebedev via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f099330094d68d268e366defffccf4c311427e67
      https://github.com/llvm/llvm-project/commit/f099330094d68d268e366defffccf4c311427e67
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    A llvm/test/Transforms/Reassociate/add-like-or.ll

  Log Message:
  -----------
  [NFC][Reassociate] Add tests with `add`-like `or` (w/ no common bits set)


  Commit: 70472f34b289d663a9f70740dfc9ae32fc89e077
      https://github.com/llvm/llvm-project/commit/70472f34b289d663a9f70740dfc9ae32fc89e077
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M llvm/lib/Transforms/Scalar/Reassociate.cpp
    M llvm/test/Transforms/Reassociate/add-like-or.ll

  Log Message:
  -----------
  [Reassociate] Convert `add`-like `or`'s into an `add`'s to allow reassociation

InstCombine is quite aggressive in doing the opposite transform,
folding `add` of operands with no common bits set into an `or`,
and that not many things support that new pattern..

In this case, teaching Reassociate about it is easy,
there's preexisting art for `sub`/`shl`:
just convert such an `or` into an `add`:
https://rise4fun.com/Alive/Xlyv


Compare: https://github.com/llvm/llvm-project/compare/36480657d8ce...70472f34b289