[all-commits] [llvm/llvm-project] 9ac291: [RISCV] Make SelectRORIW handle the commutability ...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 9ac291009356b789010f297dcf064490201c2f84
      https://github.com/llvm/llvm-project/commit/9ac291009356b789010f297dcf064490201c2f84
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-02 (Mon, 02 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rv64Zbbp.ll

  Log Message:
  -----------
  [RISCV] Make SelectRORIW handle the commutability of OR.

The SHL and SRL could be in opposite order so account for that.

Differential Revision: https://reviews.llvm.org/D90586