[all-commits] [llvm/llvm-project] 7142ec: [RISCV] When matching RORIW, make sure the same in...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 7142ec3aaf55f22e9de69fc15bba61cee9b694e0
      https://github.com/llvm/llvm-project/commit/7142ec3aaf55f22e9de69fc15bba61cee9b694e0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-02 (Mon, 02 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rv64Zbbp.ll

  Log Message:
  -----------
  [RISCV] When matching RORIW, make sure the same input is given to both shifts.

The code is looking for (sext_inreg (or (shl X, C2), (shr (and Y, C3), C1))).
We need to ensure X and Y are the same.

Differential Revision: https://reviews.llvm.org/D90580