[all-commits] [llvm/llvm-project] cc96a8: [TableGen][SchedModels] Fix read/write variant sub...

[eleviant via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: cc96a822917c1d95312a1fdb24e1fc0d5fc925b5
      https://github.com/llvm/llvm-project/commit/cc96a822917c1d95312a1fdb24e1fc0d5fc925b5
  Author: Evgeny Leviant <eleviant at accesssoftek.com>
  Date:   2020-11-02 (Mon, 02 Nov 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMScheduleA57.td
    M llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
    M llvm/utils/TableGen/CodeGenSchedule.cpp

  Log Message:
  -----------
  [TableGen][SchedModels] Fix read/write variant substitution

Patch fixes case when sched class has write and read variants belonging
to different processor models.

Differential revision: https://reviews.llvm.org/D89777