[all-commits] [llvm/llvm-project] 36920d: [RISCV] Avoid std::pair<> in FPReg StringSwitch to...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 36920d5f9d3171a91ac43cba5580635d78fe6709
      https://github.com/llvm/llvm-project/commit/36920d5f9d3171a91ac43cba5580635d78fe6709
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-11-02 (Mon, 02 Nov 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] Avoid std::pair<> in FPReg StringSwitch to avoid MSVC compile failures. NFCI.

As discussed on D90322, some MSVC builds are failing with is_trivially_copyable static asserts (see D86126) - we can avoid this by not using the std::pair<unsigned,unsigned> which held both the FP+DP Registers, just handle the FP register and convert to DP on the fly.


  Commit: b51b424c679f57dd65d83652f3e62ac2cf6de738
      https://github.com/llvm/llvm-project/commit/b51b424c679f57dd65d83652f3e62ac2cf6de738
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-11-02 (Mon, 02 Nov 2020)

  Changed paths:
    M llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll

  Log Message:
  -----------
  [SLP][X86] Add AVX512VL test target coverage for PR47629

As suggested on D90445 - the AVX512F test case alone won't handle 128/256-bit vector gather pattern very well


Compare: https://github.com/llvm/llvm-project/compare/9ffb5b0469ae...b51b424c679f