[all-commits] [llvm/llvm-project] 5547d6: [RISCV] Add more rev32 and rev16 test cases using ...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 5547d69e541d5587c7982fed4753f14c4ee85f35
      https://github.com/llvm/llvm-project/commit/5547d69e541d5587c7982fed4753f14c4ee85f35
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-01 (Sun, 01 Nov 2020)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv32Zbp.ll
    M llvm/test/CodeGen/RISCV/rv64Zbp.ll

  Log Message:
  -----------
  [RISCV] Add more rev32 and rev16 test cases using fshl/fshr intrinsics. NFC

fshl/fshr intrinsics turn into rotl/rotr ISD opcodes and we don't
have a complete set of patterns.

We pattern match rotl, but we have a custom match for rori that gets
priority. We don't pattern match rotr and we don't have patterns
or custom code for rori from rotr.


  Commit: 530bc22f280e31a00f3845baee905a77424a1e6b
      https://github.com/llvm/llvm-project/commit/530bc22f280e31a00f3845baee905a77424a1e6b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-01 (Sun, 01 Nov 2020)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv64Zbbp.ll

  Log Message:
  -----------
  [RISCV] Add a test case to show a bug in SelectRORIW. NFC

The function is matching (sext_inreg (or (shl X, C2), (shr (and Y, C3), C1))),
with appropriate checks for the constants to be a rotate. But it
fails to check that X and Y are the same which is also necessary.


Compare: https://github.com/llvm/llvm-project/compare/05c4ae122ea7...530bc22f280e