[all-commits] [llvm/llvm-project] 090e84: [RISCV] Add tests to show missed opportunities to ...

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 090e8472ae7e7c606ecd2bbb19bbf5ce1dc2b39b
      https://github.com/llvm/llvm-project/commit/090e8472ae7e7c606ecd2bbb19bbf5ce1dc2b39b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-11-01 (Sun, 01 Nov 2020)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv32Zbbp.ll
    M llvm/test/CodeGen/RISCV/rv64Zbbp.ll

  Log Message:
  -----------
  [RISCV] Add tests to show missed opportunities to use rori for fshr intrinsic with same inputs. NFC

The fshr intrinsic with same inputs produces rotr ISD node. The
fshl intrinsic produces rotl ISD node.

There were only test cases and isel patterns for the fshl/rotl case.
This patch adds fshr/rotr test cases.