[all-commits] [llvm/llvm-project] 58d3f0: [clang][aarch64] Address various fixed-length SVE ...

[Cullen Rhodes via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 58d3f0ea497206950d7bcb22b05d161e834e4396
      https://github.com/llvm/llvm-project/commit/58d3f0ea497206950d7bcb22b05d161e834e4396
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2020-10-30 (Fri, 30 Oct 2020)

  Changed paths:
    M clang/include/clang/Basic/DiagnosticSemaKinds.td
    M clang/lib/AST/ASTContext.cpp
    M clang/lib/Sema/SemaExpr.cpp
    M clang/test/Sema/attr-arm-sve-vector-bits.c

  Log Message:
  -----------
  [clang][aarch64] Address various fixed-length SVE vector operations

This patch adds tests and support for operations on SVE vectors created
by the 'arm_sve_vector_bits' attribute, described by the Arm C Language
Extensions (ACLE, version 00bet6, section 3.7.3.3) for SVE [1].

This covers the following:
* VLSTs support the same forms of element-wise initialization as GNU
  vectors.
* VLSTs support the same built-in C and C++ operators as GNU vectors.
* Conditional and binary expressions containing GNU and SVE vectors
  (fixed or sizeless) are invalid since the ambiguity around the result
  type affects the ABI.

No functional changes were required to support vector initialization and
operators. The functional changes are to address unsupported conditional and
binary expressions.

[1] https://developer.arm.com/documentation/100987/latest

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D88233