[all-commits] [llvm/llvm-project] d14db8: [ARM] Match MVE vqdmulh

[David Green via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d14db8c8dc980196c8847d109bd2e585c2ffeb73
      https://github.com/llvm/llvm-project/commit/d14db8c8dc980196c8847d109bd2e585c2ffeb73
  Author: David Green <david.green at arm.com>
  Date:   2020-10-30 (Fri, 30 Oct 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll

  Log Message:
  -----------
  [ARM] Match MVE vqdmulh

This adds ISel matching for a form of VQDMULH. There are several ir
patterns that we could match to that instruction, this one is for:

min(ashr(mul(sext(a), sext(b)), 7), 127)

Which is what llvm will optimize to once it has removed the max that
usually makes up the min/max saturate pattern, as in this case the
compare will always be false. The additional complication to match i32
patterns (which extend into an i64) is that the min will be a
vselect/setcc, as vmin is not supported for i64 vectors. Tablegen
patterns have also been updated to attempt to reuse the MVE_TwoOpPattern
patterns.

Differential Revision: https://reviews.llvm.org/D90096