[all-commits] [llvm/llvm-project] 541eff: [RISCV] Add test case for D90339

[Craig Topper via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 541effe08278cd726a81bb11b00ddfafcbed06fd
      https://github.com/llvm/llvm-project/commit/541effe08278cd726a81bb11b00ddfafcbed06fd
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-10-29 (Thu, 29 Oct 2020)

  Changed paths:
    A llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

  Log Message:
  -----------
  [RISCV] Add test case for D90339


  Commit: 74b078294ff974599416f4e961861dd0e8396748
      https://github.com/llvm/llvm-project/commit/74b078294ff974599416f4e961861dd0e8396748
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2020-10-29 (Thu, 29 Oct 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

  Log Message:
  -----------
  [RISCV] Improve worklist management in the DAG combine for SLLW/SRLW/SRAW

This combine makes two calls to SimplifyDemandedBits, one for the LHS and one
for the RHS. If the LHS call returns true, we don't make the RHS call. When
SimplifyDemandedBits makes a change, it will add the nodes around the change to
the DAG combiner worklist. If the simplification happens on the first recursion
step, the N will get added to the worklist. But if the simplification happens
deeper in the recursion, then N will not be revisited until the next time the
DAG combiner runs.

This patch explicitly addes N to the worklist anytime a Simplification is made.
Without this we might miss additional simplifications on the LHS or never
simplify the RHS. Special care also needs to be taken to not add N if it has
been CSEd by the simplification. There are similar examples in DAGCombiner and
the X86 target, but I don't have a test for it for RISC-V. I've also returned
SDValue(N, 0) instead of SDValue() so DAGCombiner knows a change was made and
will update its Statistic variable.

The test here was constructed so that 2 simplifications happen to the LHS.
Without this fix one happens in the post type legalization DAG combine and the
other happens after LegalizeDAG. This prevents the RHS from ever being
simplified causing the left and right shift to clear the upper 32 bits of the
RHS to be left behind.

Differential Revision: https://reviews.llvm.org/D90339


Compare: https://github.com/llvm/llvm-project/compare/c8c07b76b2cf...74b078294ff9