[all-commits] [llvm/llvm-project] b9c21d: RegAlloc: Clear isSSA

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: b9c21d43bb0c9e1a6d51f624f4369c717516a459
      https://github.com/llvm/llvm-project/commit/b9c21d43bb0c9e1a6d51f624f4369c717516a459
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-10-28 (Wed, 28 Oct 2020)

  Changed paths:
    M llvm/lib/CodeGen/RegAllocBasic.cpp
    M llvm/lib/CodeGen/RegAllocFast.cpp
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/lib/CodeGen/RegAllocPBQP.cpp
    A llvm/test/CodeGen/AMDGPU/greedy-broken-ssa-verifier-error.mir

  Log Message:
  -----------
  RegAlloc: Clear isSSA

The MIR parser may infer SSA, so -run-pass=regallocgreedy would hit a
verifier error after multiple vreg defs are added.