[all-commits] [llvm/llvm-project] a4fc18: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to...

[eleviant via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: a4fc18e6410f1d88ef3171e4eb6afc33d750f69a
      https://github.com/llvm/llvm-project/commit/a4fc18e6410f1d88ef3171e4eb6afc33d750f69a
  Author: Evgeny Leviant <eleviant at accesssoftek.com>
  Date:   2020-10-26 (Mon, 26 Oct 2020)

  Changed paths:
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
    M llvm/lib/Target/ARM/ARMSchedule.td
    M llvm/lib/Target/ARM/ARMScheduleA57.td
    M llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s

  Log Message:
  -----------
  [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate

Differential revision: https://reviews.llvm.org/D90029