[all-commits] [llvm/llvm-project] 68ac02: [DebugInstrRef] Pass DBG_INSTR_REFs through regist...

[Jeremy Morse via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 68ac02c0dd2b8fda52ac132a86f72f2ad6b139a5
      https://github.com/llvm/llvm-project/commit/68ac02c0dd2b8fda52ac132a86f72f2ad6b139a5
  Author: Jeremy Morse <jeremy.morse at sony.com>
  Date:   2020-10-22 (Thu, 22 Oct 2020)

  Changed paths:
    M llvm/lib/CodeGen/LiveDebugVariables.cpp
    M llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
    A llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir

  Log Message:
  -----------
  [DebugInstrRef] Pass DBG_INSTR_REFs through register allocation

Both FastRegAlloc and LiveDebugVariables/greedy need to cope with
DBG_INSTR_REFs. None of them actually need to take any action, other than
passing DBG_INSTR_REFs through: variable location information doesn't refer
to any registers at this stage.

LiveDebugVariables stashes the instruction information in a tuple, then
re-creates it later. This is only necessary as the register allocator
doesn't expect to see any debug instructions while it's working. No
equivalence classes or interval splitting is required at all!

No changes are needed for the fast register allocator, as it just ignores
debug instructions. The test added checks that both of them preserve
DBG_INSTR_REFs.

This also expands ScheduleDAGInstrs.cpp to treat DBG_INSTR_REFs the same as
DBG_VALUEs when rescheduling instructions around. The current movement of
DBG_VALUEs around is less than ideal, but it's not a regression to make
DBG_INSTR_REFs subject to the same movement.

Differential Revision: https://reviews.llvm.org/D85757