[all-commits] [llvm/llvm-project] 98797a: [PrologEpilogInserter][test] Improve SpilledToReg ...

[Fangrui Song via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 98797a5fc06c1e4885acf513d9254f285aeceeb8
      https://github.com/llvm/llvm-project/commit/98797a5fc06c1e4885acf513d9254f285aeceeb8
  Author: Fangrui Song <i at maskray.me>
  Date:   2020-10-17 (Sat, 17 Oct 2020)

  Changed paths:
    M llvm/test/CodeGen/PowerPC/prolog_vec_spills.mir

  Log Message:
  -----------
  [PrologEpilogInserter][test] Improve SpilledToReg test

D39386 made CalleeSavedInfo possible to spill a register to another register
(vector register for POWER9) but did not actually test live-in.