[all-commits] [llvm/llvm-project] 2f63e5: [MTE] Pin the tagged base pointer to one of the st...

[Evgenii Stepanov via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 2f63e57fa59e7fbfe5999ec1e6e60fa7a2ba70bb
      https://github.com/llvm/llvm-project/commit/2f63e57fa59e7fbfe5999ec1e6e60fa7a2ba70bb
  Author: Evgenii Stepanov <eugenis at google.com>
  Date:   2020-10-15 (Thu, 15 Oct 2020)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
    M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
    M llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
    M llvm/test/CodeGen/AArch64/irg_sp_tagp.ll

  Log Message:
  -----------
  [MTE] Pin the tagged base pointer to one of the stack slots.

Summary:
Pin the tagged base pointer to one of the stack slots, and (if
necessary) rewrite tag offsets so that an object that occupies that
slot has both address and tag offsets of 0. This allows ADDG
instructions for that object to be eliminated and their uses replaced
with the tagged base pointer itself.

This optimization must be done in machine instructions and not in the IR
instrumentation pass, because referring to a stack slot through an IRG
pointer would confuse the stack coloring pass.

The optimization makes a (pretty naive) attempt to find the slot that
would benefit the most by counting the uses of stack slots in the
function.

Reviewers: ostannard, pcc

Subscribers: merge_guards_bot, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72365


  Commit: 2e794a46b58c5878c5ab71c8517c5417f791860e
      https://github.com/llvm/llvm-project/commit/2e794a46b58c5878c5ab71c8517c5417f791860e
  Author: Evgenii Stepanov <eugenis at google.com>
  Date:   2020-10-15 (Thu, 15 Oct 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
    M llvm/lib/Target/AArch64/AArch64FrameLowering.h
    A llvm/test/CodeGen/AArch64/settag-merge-order.ll
    M llvm/test/CodeGen/AArch64/settag-merge.ll

  Log Message:
  -----------
  [AArch64] Stack frame reordering.

Implement stack frame reordering in the AArch64 backend.

Unlike the X86 implementation, AArch64 does not seem to benefit from
"access density" based frame reordering, mainly because it has a much
smaller variety of addressing modes, and the fact that all instructions
are 4 bytes so each frame object is either in range of an instruction
(and then the access is "free") or not (and that has a code size cost
of 4 bytes).

This change improves Memory Tagging codegen by
* Placing an object that has been chosen as the base tagged pointer of
the function at SP + 0. This saves one instruction to setup the pointer
(IRG does not have an offset immediate), and more because that object
can now be referenced without materializing its tagged address in a
scratch register.
* Placing objects that go out of scope simultaneously together. This
exposes opportunities for instruction merging in tryMergeAdjacentSTG.

Differential Revision: https://reviews.llvm.org/D72366


Compare: https://github.com/llvm/llvm-project/compare/d1beb95d1241...2e794a46b58c