[all-commits] [llvm/llvm-project] 94c18d: [VE] Add vector load/store instructions

[Kazushi Marukawa via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 94c18d91d24355ba7274c4f40f3e8754a5f72c41
      https://github.com/llvm/llvm-project/commit/94c18d91d24355ba7274c4f40f3e8754a5f72c41
  Author: Kazushi (Jam) Marukawa <marukawa at nec.com>
  Date:   2020-10-15 (Thu, 15 Oct 2020)

  Changed paths:
    M llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
    M llvm/lib/Target/VE/VEISelLowering.cpp
    M llvm/lib/Target/VE/VEInstrFormats.td
    M llvm/lib/Target/VE/VEInstrInfo.h
    M llvm/lib/Target/VE/VEInstrInfo.td
    A llvm/lib/Target/VE/VEInstrVec.td
    M llvm/lib/Target/VE/VERegisterInfo.td
    A llvm/test/MC/VE/VLD.s
    A llvm/test/MC/VE/VST.s

  Log Message:
  -----------
  [VE] Add vector load/store instructions

Add vector registers and vector load/store instructions.  Add
regression tests for vector load/store instructions too.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D89183