[all-commits] [llvm/llvm-project] 78ccb0: [AArch64][GlobalISel] Don't use explicit zero regi...

[AE via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 78ccb0359d8da3269636d85933dd8afe50a2211f
      https://github.com/llvm/llvm-project/commit/78ccb0359d8da3269636d85933dd8afe50a2211f
  Author: Amara Emerson <amara at apple.com>
  Date:   2020-10-14 (Wed, 14 Oct 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-shifted-reg-compare.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-arith-immed-compare.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Don't use explicit zero registers for compare results.

These cause problems for later optimizations, just using an unused vreg like
SelectionDAG generates better code in the end, and obviates the need for some
GISel specific flag optimizations.

Differential Revision: https://reviews.llvm.org/D89419