[all-commits] [llvm/llvm-project] 7271c1: [DDR] Introduce implicit equality check for the so...

[Roman Dzhabarov via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 7271c1bcb96051bcd227d3fa6071a620fe238850
      https://github.com/llvm/llvm-project/commit/7271c1bcb96051bcd227d3fa6071a620fe238850
  Author: rdzhabarov <rdzhabarov at google.com>
  Date:   2020-10-13 (Tue, 13 Oct 2020)

  Changed paths:
    M mlir/include/mlir/TableGen/Pattern.h
    M mlir/lib/TableGen/Pattern.cpp
    M mlir/test/lib/Dialect/Test/TestOps.td
    M mlir/test/mlir-tblgen/pattern.mlir
    M mlir/tools/mlir-tblgen/RewriterGen.cpp

  Log Message:
  -----------
  [DDR] Introduce implicit equality check for the source pattern operands with the same name.

This CL allows user to specify the same name for the operands in the source pattern which implicitly enforces equality on operands with the same name.
E.g., Pat<(OpA $a, $b, $a) ... > would create a matching rule for checking equality for the first and the last operands. Equality of the operands is enforced at any depth, e.g., OpA ($a, $b, OpB($a, $c, OpC ($a))).

Example usage: Pat<(Reshape $arg0, (Shape $arg0)), (replaceWithValue $arg0)>

Note, this feature only covers operands but not attributes.
Current use cases are based on the operand equality and explicitly add the constraint into the pattern. Attribute equality will be worked out on the different CL.

Differential Revision: https://reviews.llvm.org/D89254