[all-commits] [llvm/llvm-project] 5df617: [InstCombine] Support uniform vector splats in (((...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 5df61724a171710570f37938eb229401fa0176c7
      https://github.com/llvm/llvm-project/commit/5df61724a171710570f37938eb229401fa0176c7
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-10-13 (Tue, 13 Oct 2020)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
    M llvm/test/Transforms/InstCombine/pr19420.ll

  Log Message:
  -----------
  [InstCombine] Support uniform vector splats in ((((X >> C) & CC) + Y) << C) folds.

Add support for uniform vector splats (no undefs).


  Commit: 6c23cbc5603cf0011f8d57b0354954aeca695daf
      https://github.com/llvm/llvm-project/commit/6c23cbc5603cf0011f8d57b0354954aeca695daf
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2020-10-13 (Tue, 13 Oct 2020)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsX86.def
    M clang/lib/CodeGen/CGBuiltin.cpp
    M clang/lib/Headers/avx512fintrin.h
    M clang/test/CodeGen/X86/avx512-reduceIntrin.c
    M clang/test/CodeGen/X86/avx512-reduceMinMaxIntrin.c

  Log Message:
  -----------
  [X86] Convert integer _mm_reduce_* intrinsics to emit llvm.reduction intrinsics (PR47506)

Emit the equivalent integer reduction intrinsics in IR instead of expanding to shuffle+arithmetic sequences.

The fadd/fmul reductions might be trickier as they assume a similar bisection reduction while the generic intrinsics assume a sequential reduction (intel docs are ambiguous on the correct approach) - I'm not sure if we want to always tag them with reassoc? Anyway, that issue can wait until a separate fp patch along with the fmin/fmax reductions.

Differential Revision: https://reviews.llvm.org/D87604


Compare: https://github.com/llvm/llvm-project/compare/06a5e2f30789...6c23cbc5603c