[all-commits] [llvm/llvm-project] ed88d9: [RISCV] Use the extensions in the canonical order ...

[Evandro Menezes via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: ed88d962953c52c76d568d90fe2d5546ea6ab543
      https://github.com/llvm/llvm-project/commit/ed88d962953c52c76d568d90fe2d5546ea6ab543
  Author: Evandro Menezes <ebahapo at users.noreply.github.com>
  Date:   2020-10-05 (Mon, 05 Oct 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td

  Log Message:
  -----------
  [RISCV] Use the extensions in the canonical order (NFC)

Fix a mistake in the ordering.


  Commit: 5d6d8a2769b3a91fd65b125c2cda64ea27a894bf
      https://github.com/llvm/llvm-project/commit/5d6d8a2769b3a91fd65b125c2cda64ea27a894bf
  Author: Evandro Menezes <ebahapo at users.noreply.github.com>
  Date:   2020-10-05 (Mon, 05 Oct 2020)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note.c
    M llvm/include/llvm/Support/RISCVTargetParser.def
    M llvm/lib/Target/RISCV/RISCV.td

  Log Message:
  -----------
  [RISCV] Add SiFive cores to the CPU option

Add the SiFive cores E76 and U74 using the SiFive 7 series microarchitecture.

Differential Revision: https://reviews.llvm.org/D88759


Compare: https://github.com/llvm/llvm-project/compare/477a68760b24...5d6d8a2769b3