[all-commits] [llvm/llvm-project] e2ccf7: [SVE] Lower fixed length VECREDUCE_[SMAX|SMIN] to ...

[Cameron McInally via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: e2ccf7f178ddaf202171a96cd6f41daa7a74a09c
      https://github.com/llvm/llvm-project/commit/e2ccf7f178ddaf202171a96cd6f41daa7a74a09c
  Author: Cameron McInally <mcinally at cray.com>
  Date:   2020-09-25 (Fri, 25 Sep 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll

  Log Message:
  -----------
  [SVE] Lower fixed length VECREDUCE_[SMAX|SMIN] to Scalable

This patch is pretty similar to the VECREDUCE_ADD patch, with some minor tweaks.

Results from the AArch64ISD::[SMAX|SMIN]V_PRED return element sized results. This requires an ANY_EXTEND for results < 32-bits, since Legalization promotes those results.

There is no NEON i64 vector support for SMAXV|SMINV, so use SVE for those.

Differential Revision: https://reviews.llvm.org/D88259