[all-commits] [llvm/llvm-project] af0207: AMDGPU: Check global FP atomics match default FP mode

[Matt Arsenault via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: af0207f2bae8578c5283877a786e502ce6e33b14
      https://github.com/llvm/llvm-project/commit/af0207f2bae8578c5283877a786e502ce6e33b14
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-09-23 (Wed, 23 Sep 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/global-atomics-fp.ll
    M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll

  Log Message:
  -----------
  AMDGPU: Check global FP atomics match default FP mode

We would always select global FP atomics from atomicrmw fadd, although
they have a hardcoded FP mode.


  Commit: c463fd136ec259ec269ee6741763ce595811da71
      https://github.com/llvm/llvm-project/commit/c463fd136ec259ec269ee6741763ce595811da71
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2020-09-23 (Wed, 23 Sep 2020)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
    A llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shl.mir

  Log Message:
  -----------
  GlobalISel: Fix truncating shift amount in trunc (shl) combine

The shift amount type does not necessarily match the result type. This
was inserting a trunc from s32 to s32, which asserted. Just preserve
the original shift amount type which can be legalized later.


Compare: https://github.com/llvm/llvm-project/compare/20f84257ac4a...c463fd136ec2