[all-commits] [llvm/llvm-project] d0149b: [SVE][CodeGen] Lower legal integer -> floating poi...

[kmclaughlin-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: d0149ba9b46d6ca08b29c9a820b5cb772c799211
      https://github.com/llvm/llvm-project/commit/d0149ba9b46d6ca08b29c9a820b5cb772c799211
  Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
  Date:   2020-09-23 (Wed, 23 Sep 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-fcvt.ll

  Log Message:
  -----------
  [SVE][CodeGen] Lower legal integer -> floating point conversions

This patch adds new ISD nodes, SCVTZ_MERGE_PASSTHRU &
UCVTZ_MERGE_PASSTHRU, which are used to lower both legal
scalable vector [S|U]INT_TO_FP operations and the following intrinsics:
 - llvm.aarch64.sve.scvtf
 - llvm.aarch64.sve.ucvtf

Reviewed By: sdesmalen, efriedma

Differential Revision: https://reviews.llvm.org/D87913