[all-commits] [llvm/llvm-project] 394d02: [RISCV] Do not mandate scheduling for CSR instruct...

[Evandro Menezes via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 394d02016705e4b0fdfaa34c53be695f3f61922d
      https://github.com/llvm/llvm-project/commit/394d02016705e4b0fdfaa34c53be695f3f61922d
  Author: Evandro Menezes <ebahapo at users.noreply.github.com>
  Date:   2020-09-21 (Mon, 21 Sep 2020)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td

  Log Message:
  -----------
  [RISCV] Do not mandate scheduling for CSR instructions

Scheduling information is of little value when they may disrupt the
pipeline.  This patch allows omitting the scheduling information for CSR
instructions while still setting `SchedMachineModel::CompleteModel`.  For
specific cases, any scheduling information added will be used by the
scheduler.

Differential revision: https://reviews.llvm.org/D85366