[all-commits] [llvm/llvm-project] 1372e2: [PowerPC] Add vector pair load/store instructions ...

[bsaleil via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: 1372e23c7d4b25fd23689842246e66f70c949b46
      https://github.com/llvm/llvm-project/commit/1372e23c7d4b25fd23689842246e66f70c949b46
  Author: Baptiste Saleil <baptiste.saleil at ibm.com>
  Date:   2020-09-21 (Mon, 21 Sep 2020)

  Changed paths:
    M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
    M llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
    M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
    M llvm/lib/Target/PowerPC/PPCInstrPrefix.td
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.h
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
    M llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
    M llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
    M llvm/utils/TableGen/CodeGenTarget.cpp

  Log Message:
  -----------
  [PowerPC] Add vector pair load/store instructions and vector pair register class

This patch adds support for the lxvp, lxvpx, plxvp, stxvp, stxvpx and pstxvp
instructions in the PowerPC backend. These instructions allow loading and
storing VSX register pairs. This patch also adds the VSRp register class
definition needed for these instructions.

Differential Revision: https://reviews.llvm.org/D84359