[all-commits] [llvm/llvm-project] f3fa95: [SVE] Change definition of reduction ISD nodes to ...

[paulwalker-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f3fa954b5b19acdd4b95ff2ca1ff4f74f4b6b21b
      https://github.com/llvm/llvm-project/commit/f3fa954b5b19acdd4b95ff2ca1ff4f74f4b6b21b
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2020-09-21 (Mon, 21 Sep 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-int-reduce-pred.ll

  Log Message:
  -----------
  [SVE] Change definition of reduction ISD nodes to have an SVE vector result type.

The current nodes, AArch64::SMAXV_PRED for example, are defined to
return a NEON vector result.  This is incorrect because they modify
the complete SVE register and are thus changed to represent such.

This patch also adds nodes for UADDV_PRED and SADDV_PRED, which
unifies the handling of all SVE reductions.

NOTE: Floating-point reductions are already implemented correctly,
so this patch is essentially making everything consistent with those.

Differential Revision: https://reviews.llvm.org/D87843