[all-commits] [llvm/llvm-project] c3492a: [amdgpu] Lower SGPR-to-VGPR copy in the final phas...

[darkbuck via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: c3492a1aa1b98c8d81b0969d52cea7681f0624c2
      https://github.com/llvm/llvm-project/commit/c3492a1aa1b98c8d81b0969d52cea7681f0624c2
  Author: Michael Liao <michael.hliao at gmail.com>
  Date:   2020-09-17 (Thu, 17 Sep 2020)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/fabs.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
    A llvm/test/CodeGen/AMDGPU/sgpr-copy-cse.ll
    M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
    M llvm/test/CodeGen/AMDGPU/wqm.ll

  Log Message:
  -----------
  [amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel.

- Need to lower COPY from SGPR to VGPR to a real instruction as the
  standard COPY is used where the source and destination are from the
  same register bank so that we potentially coalesc them together and
  save one COPY. Considering that, backend optimizations, such as CSE,
  won't handle them. However, the copy from SGPR to VGPR always needs
  materializing to a native instruction, it should be lowered into a
  real one before other backend optimizations.

Differential Revision: https://reviews.llvm.org/D87556