[all-commits] [llvm/llvm-project] f7185b: [SVE][CodeGen] Lower floating point -> integer con...

[kmclaughlin-arm via All-commits]

  Branch: refs/heads/master
  Home:   https://github.com/llvm/llvm-project
  Commit: f7185b271f5b3010c82a56417b437f2a44a79230
      https://github.com/llvm/llvm-project/commit/f7185b271f5b3010c82a56417b437f2a44a79230
  Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
  Date:   2020-09-17 (Thu, 17 Sep 2020)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/CodeGen/AArch64/sve-fcvt.ll
    A llvm/test/CodeGen/AArch64/sve-split-fcvt.ll

  Log Message:
  -----------
  [SVE][CodeGen] Lower floating point -> integer conversions

This patch adds new ISD nodes, FCVTZS_MERGE_PASSTHRU &
FCVTZU_MERGE_PASSTHRU, which are used to lower scalable vector
FP_TO_SINT/FP_TO_UINT operations and the following intrinsics:
 - llvm.aarch64.sve.fcvtzu
 - llvm.aarch64.sve.fcvtzs

Reviewed By: efriedma, paulwalker-arm

Differential Revision: https://reviews.llvm.org/D87232